In a package mounting structure, electronic components such as a central processing unit (CPU) package, a memory, an input and output (I/O) portion, a power supply portion and a connector, are separately implemented on a system board (motherboard). A cooler is attached to the CPU package, the memory, the I/O portion, and the power supply portion, if desired.
On the system board, the CPU package and the power supply portion are horizontally placed. Inside the system board, a power supply path is arranged and power is supplied to the CPU. Furthermore, from a demand for high speed transmission, there are considerations that the memory and the I/O portion are mounted on the CPU package, and the memory and the I/O portion are positioned close to the CPU.
In recent years, while power consumption of the CPU or the memory increases, an operating voltage tends to be low. Therefore, a supply current value to the CPU or the memory becomes large, and a voltage drop (drop in a power supply voltage) is generated due to sheet resistance in case of supplying the power to the CPU through the power supply path inside the system board.
Moreover, inside the system board, a via for transmitting a signal from the CPU package is arranged. When the via for the signal intersects with a power layer inside the system board and a ground layer, a clearance is set on the power layer and the ground layer. If the clearance is set on the power layer and the ground layer, areas for the power layer and the ground layer decrease, and the voltage drop increases. If the via for the signal is arranged outside of the power layer and the ground layer so that the via for the signal does not intersect with the power layer and the ground layer, a signal terminal of a package substrate is also extended outside thereof and the area of the package substrate becomes large.
The following are reference documents.                [Document 1] Japanese Examined Utility Model Registration Application Publication No. 62-32592,        [Document 2] Japanese Laid-open Patent Publication No. 2010-267945, and        [Document 3] Japanese Laid-open Patent Publication No. 2001-53206.        